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Between 2026-06-30 11:59 p.m. and 2026-08-01 12:00 a.m.
MINTIMESTEPSBP and the tolerance tunables please to dial in a minimum of actually to-be-taken timesteps that would still be expected to give meaningful results.
A full nonlin solve there didn't take thaaaat long:
***** Solution Summary *****
Number Successful Steps Taken: 1
Number Failed Steps Attempted: 0
Number Jacobians Evaluated: 362
Number Linear Solves: 362
Number Failed Linear Solves: 0
Number Linear Solver Iterations: 70583
Number Residual Evaluations: 373
Number Nonlinear Convergence Failures: 0
Total Residual Load Time: 78.2002 seconds
Total Jacobian Load Time: 61.0558 seconds
Total Linear Solution Time: 1952.14 seconds
***** Total Simulation Solvers Run Time: 2152.39 seconds
***** Total Elapsed Run Time: 2247.1 seconds
*****.option timeint ERROPTION=1 to explicitly not use the classic SPICE "local truncation error", but instead just adjust step size based on how many newton (or whatever nonlinear solver was selected) iterations it took to turn the predictor's (the trapezoidal/backwards-euler/2nd-order-gear time integration forward-model) estimate of the solution variable's values (e.g. node voltages and a bunch of (internal) port currents) into a new solution that is newly compliant with all the non-linear device interaction models up to the configured tolerances (absolute, relative, and what the scale reference is for "relative"; sadly AFAIK there's no straight-forward way to distinguish between current and voltage quantities for that config option, which would be IMO fairly relevant for abstol as e.g. tolerance better than like a single millivolt is probably not required for this type of circuit if one wants to check against DOA and isn't trying to do fancy calibration stuff; also not to forget update-norm and unweighted l2-norm of the residual which are also tunables for deeming the nonlinear solve "sufficciently converged").*** 5. INPUT STIMULUS ***
V_clk clk VSS PULSE( 0 3.3 0 0.1ns 0.1ns 50ns 200ns )
V_clk_n clk_n VSS PULSE( 0 3.3 100ns 0.1ns 0.1ns 50ns 200ns )
V_rst_n rst_n VSS PULSE( 0 3.3 375ns 0.1ns 0.1ns 5us 6us )
V_rst_override_n rst_override_n VSS PULSE( 0 3.3 375ns 0.1ns 0.1ns 5us 6us )
And then run that for a few clock cycles and observe the outputs. This is set up for a 5us long run. .gds flattened as much as this and with no stray labels littered around, you are then allowed to have labels on internal nets of interest or I'd guess there would be some way from the LVS machinery to slap semantically meaningful labels on nets and/or devices.
I'll see to get a .nodeset-based initial conditions dump next run which should make it much faster to jump in and test things.
_dss construction perhaps able to squeeze into at least some of your cells and perhaps be less-leaky?less and rg as well....
Would be great if you could by chance confirm this clock "phasing" to be liable for severe power draw.
And if you'd perhaps be so kind as to make us a _v5.xyce by adjusting the inputs, I'd even fast-track that through Xyce over Mosh (remote shell).
https://chatgpt.com/s/t_6a5543dabbc88191a1d7f6b3f8919000 poly2 on comp, though?
din[15] connects to.
NAND and NOT .
This is highly concerning.clkbuf_8!